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Miniaturized Transistors
Lado Filipovic and Tibor Grasser
2019
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What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications.
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Keywords
- ambipolar
- band-to-band tunneling (BTBT)
- bulk NMOS devices
- buried channel
- CMOS
- compact model
- compact models
- device simulation
- doping incorporation
- drain engineered
- electrostatic discharge (ESD)
- etching simulation
- ferroelectrics
- field effect transistor
- field-effect transistor
- fin field effect transistor (FinFET)
- FinFETs
- flux calculation
- high-? dielectric
- high-k
- highly miniaturized transistor structure
- indium selenide
- inversion channel
- Layout
- level set
- line edge roughness
- low energy
- low power consumption
- low voltage
- low-frequency noise
- metal gate granularity
- metal gate stack
- metal oxide semiconductor field effect transistor (MOSFET)
- mobility
- MOS devices
- MOSFET
- n/a
- nanosheets
- nanowire
- Nanowires
- negative-capacitance
- neuromorphic system
- non-equilibrium Green’s function
- ON-state
- phonon scattering
- piezoelectrics
- plasma-aided molecular beam epitaxy (MBE)
- Polarization
- power consumption
- process simulation
- process variations
- radiation hardened by design (RHBD)
- random discrete dopants
- Segregation
- semi-floating gate
- Sentaurus TCAD
- sigE
- silicon nanowire
- Silicon-Germanium source/drain (SiGe S/D)
- silicon-on-insulator
- spike-timing-dependent plasticity (STDP)
- statistical variations
- subthreshold
- subthreshold bias range
- surface potential
- synaptic transistor
- systematic variations
- technology computer aided design (TCAD)
- technology computer-aided design (TCAD)
- theoretical model
- thin-film transistors (TFTs)
- topography simulation
- total ionizing dose (TID)
- tunnel field effect transistor (TFET)
- tunnel field-effect transistor (TFET)
- two-dimensional material
- variability
Links
DOI: 10.3390/books978-3-03921-011-4Editions
