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Advanced Interconnect and Packaging
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Unlike transistors, the continuous downscaling of feature size in CMOS technology leads to a dramatic rise in interconnect resistivity and concomitant performance degradation. At nanoscale technology nodes, interconnect delay and reliability become the major bottlenecks faced by modern integrated circuits. To resolve these interconnect problems, various emerging technologies, including airgap, nanocarbon, optical, and through-silicon via (TSV), have been proposed and investigated. For example, by virtue of TSV technology, dies can be stacked to increase the integration density. More importantly, 3D integration and packaging also offer the most promising platform to implement "More-than-Moore" technologies, providing heterogeneous materials and technologies on a single chip. The "Advanced Interconnect and Packaging" Special Issue seeks to showcase research papers on new developments in advanced interconnect and packaging, i.e., on the design, modeling, fabrication, and reliability assessment of emerging interconnect and packaging technologies. Additionally, there are two interesting papers on carbon nanotube interconnects and interconnect reliability issues.
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Keywords
- 3D IC
- Aging
- antenna current
- Au wire bonding
- Au–Au bonding
- average heat-spreading width
- average power handling capability (APHC)
- Bi aggregation
- blood oxygen
- broadband
- broadside structure
- carbon nanotube
- circuit model
- coverage thickness
- Cu-CNT composite
- Cu–Sn bonding
- deadbeat controller
- dual active bridge
- electromagnetic bandgap (EBG)
- electromigration
- far-end crosstalk
- flow time
- focused ion beam (FIB)
- frequency selective rasorber (FSR)
- frequency selective surface (FSS)
- frequency-selective surface analytical approximation
- Graphene
- high-temperature annealing
- high-temperature pressure sensor
- high-temperature resistant packaging
- hot-melt glass
- impedance
- integrated circuit interconnects
- integrated passive device
- interposer channel
- interposers
- kinetic inductance
- load feedforward
- low-loss substrates
- low-temperature soldering
- Mathematical model
- Mathematics & science
- MEMS sensor
- metallic bonding
- morphology analysis
- n/a
- noise suppression structures
- on-chip interconnect
- on-chip spiral inductor
- packages
- parylene
- Physics
- physics-based modeling
- power delivery network (PDN)
- power/ground noise
- Pt–Pt interconnection
- quantum resistance
- Reference, information & interdisciplinary subjects
- Reliability
- reliability evaluation
- Research & information: general
- sensing array
- silicon interposer
- SiO2 and Au substrate
- slow-wave transmission line (SWTL)
- Sn-Bi solder
- spoof surface plasmon polaritons (SSPP)
- spoof surface plasmon polaritons (SSPPs)
- substrate integrated waveguide (SIW)
- temperature-dependent resistivity
- thermal resistance
- through-dielectric capacitor (TDC)
- through-silicon-via (TSV)
- transmission line model
- vacuum degradation
- vertical tabbed via
- Wearable Device
- wettability
Links
DOI: 10.3390/books978-3-0365-6732-7Editions